1. Field of the Invention
The present invention relates to the field of charge pumps.
2. Prior Art
Charge pumps are well known in the prior art for operating from a power supply of a first voltage for such purposes as providing a source of power at a second voltage higher than the first voltage (voltage multiplication), and/or providing a balanced (plus and minus) power supply from a single power supply (voltage inversion). Such charge pumps are often realized in integrated circuit form and the output thereof used for various purposes on that integrated circuit. By way of a specific example, the preferred embodiment of the present invention is intended for use in CMOS integrated circuits to provide an augmented dual supply to achieve rail-to-rail input and rail-to-rail output voltages for on chip integrated circuits.
A typical circuit for a prior art voltage mode charge pump may be seen in FIG. 1. As shown in that Figure, fly capacitors C.sub.1 and C.sub.2 are driven by a clock signal CLK through inverters INV1, INV2 and INV3. The inverters are shown schematically, in that the output of the inverters INV1 and INV2 are non-overlapping signals representing the inverted clock signal CLK and the non-inverted clock signal, respectively. When the output of inverter INV1 is high and the output of inverter INV2 is low, the charge on capacitor C.sub.1 will drive the voltage on node 1 higher than the supply voltage V.sub.DD. This turns off n-channel transistor M1, and turns on n-channel transistor M2 to charge capacitor C.sub.2 to the power supply voltage V.sub.DD (the output of inverter INV2 being low, typically at ground potential). At the same time node 1, being driven higher than the power supply V.sub.DD, will hold p-channel device M4 off. The low voltage on node 2, however, will turn on p-channel device M3 to couple the higher voltage at node 1 to the output V.sub.OUT, delivering charge to the reserve capacitor C.sub.OUT in an amount dependent upon the value of the output voltage V.sub.OUT, the current being drawn by the load connected to the output V.sub.OUT and the various other parameters of the charge pump.
When the output of the inverter INV1 goes low and the output of inverter INV2 goes high, the voltage on node 2 will now go higher than the supply voltage V.sub.DD because of the charge on capacitor C.sub.2, turning on n-channel transistor M1 to recharge capacitor C.sub.1 to the voltage V.sub.DD. The voltage on node 1 will turn on p-channel device M4 to couple the higher voltage on node 2 to the output V.sub.OUT, delivering charge from fly capacitor C.sub.2 to the reserve capacitor C.sub.OUT. Note that even if the voltage on node 1 is equal to V.sub.DD, as it would be when capacitor C.sub.1 is fully charged, the voltage on node 2 when the output of inverter INV2 is high, and the output voltage V.sub.OUT, will both be higher than the voltage V.sub.DD, SO that both the source and drain of p-channel device M4 will be at higher voltages than the gate of the device. With no significant load on the output of the charge pump, the output voltage V.sub.OUT will stabilize at approximately 2 V.sub.DD.
In the foregoing circuit, the power consumption is not well controlled due to switching losses, namely the feed through current in inverters INV1, INV2 and INV3. Also the excess current required to charge and discharge the capacitors due to the switching times.